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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">EDCIDSR, External Debug Context ID Sample Register</h1><p>The EDCIDSR characteristics are:</p><h2>Purpose</h2>
        <p>Contains the sampled value of the Context ID, captured on reading <a href="ext-edpcsr.html">EDPCSR</a>[31:0].</p>
      <h2>Configuration</h2><p>EDCIDSR is in the Core power domain.
    </p><p>This register is present only when FEAT_PCSRv8 is implemented and FEAT_PCSRv8p2 is not implemented. Otherwise, direct accesses to EDCIDSR are <span class="arm-defined-word">RES0</span>.</p>
        <p>Implemented only if the <span class="arm-defined-word">OPTIONAL</span> PC Sample-based Profiling Extension is implemented in the external debug registers space.</p>

      
        <div class="note"><span class="note-header">Note</span><p><span class="xref">FEAT_PCSRv8p2</span> implements the PC Sample-based Profiling Extension in the Performance Monitors registers space.</p></div>
      <h2>Attributes</h2>
        <p>EDCIDSR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-31_0">CONTEXTIDR</a></td></tr></tbody></table><h4 id="fieldset_0-31_0">CONTEXTIDR, bits [31:0]</h4><div class="field"><p>Context ID. The value of <span class="xref">CONTEXTIDR</span> that is associated with the most recent <a href="ext-edpcsr.html">EDPCSR</a> sample. When the most recent <a href="ext-edpcsr.html">EDPCSR</a> sample is generated:</p>
<ul>
<li>If EL1 is using AArch64, then the Context ID is sampled from <a href="AArch64-contextidr_el1.html">CONTEXTIDR_EL1</a>.
</li><li>If EL1 is using AArch32, then the Context ID is sampled from <a href="AArch32-contextidr.html">CONTEXTIDR</a>.
</li><li>If EL3 is implemented and is using AArch32, then <a href="AArch32-contextidr.html">CONTEXTIDR</a> is a banked register, and EDCIDSR samples the current banked copy of <a href="AArch32-contextidr.html">CONTEXTIDR</a> for the Security state that is associated with the most recent <a href="ext-edpcsr.html">EDPCSR</a> sample.
</li></ul>
<p>Because the value written to EDCIDSR is an indirect read of <span class="xref">CONTEXTIDR</span>, it is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> whether EDCIDSR is set to the original or new value if <a href="ext-edpcsr.html">EDPCSR</a> samples:</p>
<ul>
<li>An instruction that writes to <span class="xref">CONTEXTIDR</span>.
</li><li>The next Context synchronization event.
</li><li>Any instruction executed between these two instructions.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing EDCIDSR</h2>
        <p><span class="arm-defined-word">IMPLEMENTATION DEFINED</span> extensions to external debug might make the value of this register <span class="arm-defined-word">UNKNOWN</span>, see <span class="xref">'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'</span>.</p>
      <h4>EDCIDSR can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>Debug</td><td><span class="hexnumber">0x0A4</span></td><td>EDCIDSR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When IsCorePowered(), !DoubleLockStatus() and !OSLockStatus(), accesses to this register are <span class="access_level">RO</span>.
          </li><li>Otherwise, accesses to this register generate an error response.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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